1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of etching a doped polysilicon layer.
2. Description of the Related Art
Progress in semiconductor fabrication technologies has made it possible to fabricate semiconductor devices at the deep sub-micron level. In deep sub-micron semiconductor technology, the required gate sizes are specifically small and the required operation voltages are high. Thus, gate material has to be improved in order to maintain gate stability. However, reduction size of the gate may cause a short channel effect to occur. A dual gate comprises gates of different conductive types. Because the dual gate has good control ability to withstand the short channel effect, it has become widely used in a gate fabricating process with a linewidth of about 0.25 micro meter to 0.18 micro meter.
An N-type polysilicon gate and a P-type polysilicon gate are both employed in the dual gate structure. Therefore, it is desired to etch simultaneously an N-type polysilicon layer and a P-type polysilicon layer during an etching process to form a dual gate. Due to different doping concentrations and different conductive types of the N-type polysilicon layer and the P-type polysilicon layer, the etching rates of the N-type polysilicon layer and the P-type polysilicon layer are different. The different etching rates cause significantly high etching bias on the N-type polysilicon layer the P-type polysilicon layer, which significantly increases risks of device failure.
Reference is made to FIG. 1, which explains a dual gate formed by etching a doped polysilicon layer having an N-type polysilicon gate and a P-type polysilicon gate. The devices represented by each number are as follows: a substrate 100, an isolation structure 102, an N-well 104, a P-well 106, a gate oxide layer 108, a P-type polysilicon gate 110, and an N-type polysilicon gate 112.
The etching rate of the N-type polysilicon is higher than the etching rate of the P-type polysilicon, which easily leads to an etching bias. As shown in FIG. 1, after the etching process, the gate oxide layer 108 beside the N-type polysilicon gate 112 is exposed after etching, whereas the undesired portions of the P-type polysilicon gate 110 still remain to cover a portion of the gate oxide layer 108. The P-type polysilicon gate 110 is etched to leave thin edge portions of the P-type polysilicon gate 110 that covers the gate oxide layer 108. The sidewall profile of the P-type polysilicon gate 110 is different from a desired profile, which is called an etching bias, because of the remaining undesired edge portions of the P-type polysilicon gate 110. The etching bias may further cause critical dimension bias (CD bias) and reduce device integration.
If the etching step is performed until the P-type polysilicon gate 110 is completely removed, it is easy to over-etch the gate oxide layer 108 beside the N-type polysilicon gate 112. Once the N-type polysilicon gate 112 is over-etched, it is possible to punchthrough the gate oxide layer 108 beside N-type polysilicon gate layer 112. The gate oxide layer 108 may be etched until it is thin enough to form pits therein. Thus, the remaining gate oxide layer 108 is not sufficient to protect the substrate in the subsequent steps. It becomes especially serious for a fabricating process with a linewidth below 0.18 micro meter, in which the thickness of the gate oxide layer is only about 35 angstroms.